The present invention relates to semiconductor devices, and more particularly to transistors.
Transistors are widely used for switching and amplification in memories, computer processors, and other electrical circuits. In many applications, transistor current carrying elements are fabricated in a semiconductor substrate. For example, the source, drain and channel regions of a lateral MOS transistor are formed in a monocrystalline semiconductor substrate with the gate above the substrate.
In some circuits, the transistor current carrying elements are formed over the substrate. The transistor can be stacked above other circuit elements, which allows reducing the circuit area and hence increasing the packing density and reducing the manufacturing costs. Fabricating such a transistor, however, is sometimes complicated by additional masks required for transistor doping. Consider, for example, a lateral MOS silicon transistor with the source, drain and channel regions formed over the substrate. Because of the limitations of fabrication technology, the source, drain and channel regions are typically formed in polycrystalline silicon rather than monocrystalline silicon. As is well known, such transistors suffer from poor differentiation between the ON and OFF currents. The current differentiation can be improved by providing an LDD (lightly doped drain) structure that is not symmetric on the source and drain sides. For example, in some transistors, an LDD structure is provided on the drain side but not on the source side because an LDD structure on the drain side significantly improves the ON/OFF current differentiation but an LDD structure on the source side does not provide a similar improvement but does reduce the ON current. An asymmetric LDD structure typically cannot be manufactured by the conventional self-aligned method of forming a transistor with source, drain and channel regions in the substrate which method involves a blanket etch of a conformal layer to form spacers on the gate sidewalls, because the spacers, which are used as a mask for heavy source/drain doping, are typically symmetric on the source and drain sides. Therefore a separate mask is required for heavy source/drain doping. Moreover, the conventional method is unavailable for either symmetric or asymmetric LDD structures if the transistor gate is formed below the channel region rather than above the channel region. (The gate may be formed below the channel region in order, for example, to facilitate the gate connection to other circuit elements formed below the channel region.) In addition, if the gate is formed below the channel region, the gate itself is unavailable as a mask for the LDD doping, and hence still another mask is required.
The additional masks require additional alignments which affect transistor critical dimensions such as the channel length and which therefore necessitate increased transistor area to meet the minimum critical dimension requirements such as the minimum channel length requirement. Moreover, the transistor electrical characteristics become difficult to reproduce due to critical dimension variations caused by the additional alignments. Low reproducibility leads in turn to a low circuit yield.
There is a need therefore for a transistor fabrication method in which fewer masks affect the critical dimensions such as the channel length, so that one could achieve a smaller transistor area, a greater reproducibility, and a higher yield.